N- BIT COUNTER

See VHDL code for the N-Bit counter

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.NUMERIC_STD.ALL;

ENTITY nbit_counter IS
    GENERIC (
        BIT_WIDTH :integer    );
PORT (
 clk     : IN STD_LOGIC;
 reset_n : IN STD_LOGIC;
 up_down : IN STD_LOGIC;
 counter : OUT STD_LOGIC_VECTOR( BIT_WIDTH -1 DOWNTO 0)
 );
END nbit_counter;

ARCHITECTURE Arch OF nbit_counter IS
SIGNAL s_counter  : UNSIGNED( BIT_WIDTH -1 DOWNTO 0);
BEGIN

-- COMBINATIONAL ASSIGNMENTS
counter <= STD_LOGIC_VECTOR(s_counter);

P_counter : PROCESS(clk,reset_n)
  BEGIN
    IF (reset_n = '0') THEN
      s_counter <= (OTHERS => '0');
    ELSIF RISING_EDGE(clk) THEN
      IF ( up_down = '1' ) THEN
        s_counter <= s_counter + "1";
      ELSE
        s_counter <= s_counter - "1";
      END IF;
    END IF;
END PROCESS  P_counter;

 END Arch;

See simulation waveform below..