Divide By 7 Clock with 50% Duty Cycle

RTL Code


-----------------------------------------------------------------
-- File Name : divide_by7.vhd
-----------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.NUMERIC_STD.ALL;

ENTITY divide_by7 IS
PORT (
 clk      : IN  STD_LOGIC                              ;
 reset_n  : IN  STD_LOGIC                              ;
 o_clk_by7: OUT STD_LOGIC                      
 );
END divide_by7;

ARCHITECTURE Arch OF divide_by7 IS
SIGNAL COUNTER : UNSIGNED(2 DOWNTO 0);
SIGNAL div_1   : STD_LOGIC;
SIGNAL div_2   : STD_LOGIC;
SIGNAL clk_low_cnt   : STD_LOGIC;
SIGNAL clk_high_cnt   : STD_LOGIC;

BEGIN

-- Counter generation
PROCESS(clk,reset_n)
  BEGIN
    IF (reset_n = '0') THEN
      COUNTER <= "111";
    ELSIF RISING_EDGE(clk) THEN
      IF COUNTER = "110" THEN
        COUNTER <= "000";
      ELSE
        COUNTER <=  COUNTER + 1;
      END IF;
    END IF;
END PROCESS;

-- clk_r generation
PROCESS(clk,reset_n)
  BEGIN
    IF (reset_n = '0') THEN
      clk_low_cnt  <= '0';
      clk_high_cnt <= '0';
    ELSIF RISING_EDGE(clk) THEN
      IF COUNTER = "000" THEN
        clk_low_cnt <= '1';
      ELSE
        clk_low_cnt <= '0';
      END IF;
      IF COUNTER = "100" THEN
        clk_high_cnt <= '1';
      ELSE
        clk_high_cnt <= '0';
      END IF;
    END IF;
END PROCESS;

-- div_1 generation
PROCESS(clk,reset_n)
  BEGIN
    IF (reset_n = '0') THEN
      div_1 <= '0';
    ELSIF RISING_EDGE(clk) THEN
      IF clk_low_cnt = '1' THEN
        div_1 <= NOT div_1;
      END IF;
    END IF;
  END PROCESS;

-- clk_f generation
PROCESS(clk,reset_n)
  BEGIN
    IF (reset_n = '0') THEN
      div_2 <= '0';
    ELSIF FALLING_EDGE(clk) THEN
      IF clk_high_cnt = '1' THEN
        div_2 <= NOT div_2;
      END IF;
    END IF;
  END PROCESS;

o_clk_by7 <= div_1 XOR div_2;
   
END Arch;

Test Bench

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE  IEEE.NUMERIC_STD.ALL;

ENTITY divide_by7_tb IS

END divide_by7_tb;

ARCHITECTURE tb OF divide_by7_tb IS

SIGNAL clk          : STD_LOGIC;

SIGNAL reset_n      : STD_LOGIC;

SIGNAL o_clk_by7    : STD_LOGIC;

CONSTANT PERIOD     : TIME := 5 ns;

COMPONENT divide_by7 IS

PORT (

 clk      : IN  STD_LOGIC                              ;

 reset_n  : IN  STD_LOGIC                              ;

 o_clk_by7: OUT STD_LOGIC

 );

END COMPONENT;

BEGIN

inst_divide_by7 : divide_by7

PORT MAP (

 clk      => clk      ,

 reset_n  => reset_n  ,

 o_clk_by7=> o_clk_by7

 );

  

clk_process :process

  begin

    clk <= '0';

    wait for PERIOD/2;

    clk <= '1';

    wait for PERIOD/2;

  end process;

  

  -------------------------------------------

  -- Stimulus generation

  --------------------------------------------

  stimulus: process

  begin  

    -- Put initialisation code here

    reset_n <= '0';

    wait for PERIOD;

    reset_n <= '1';

    wait for PERIOD;

    wait;

  END process;  

END tb;

Simulation waveform